Best Paper Award Finalist at DesignCon2019 for "PCB Interconnect Modeling Demystified" publication. Slides can be downloaded here.
Best Paper Award Finalist and Winner of Best Paper Award at DesignCon2018 for "A Causal Conductor Roughness Model and its Effect on Transmission Line Characteristics" publication. Slides can be downloaded here
EDICon 2017, Boston MA, "Practical Modeling of High-speed Channels Based on Data Sheet Input".
Best Paper Award Finalist at DesignCon2017 for "A Practical Method to Model Effective Permittivity and Phase Delay Due to Conductor Surface Roughness" publication.
EDICon 2016, Boston MA, "Practical Model of Conductor Surface Roughness Using Cubic Close-packing of Equal Spheres".
IEEE publication, "Practical method for modeling conductor roughness using cubic close-packing of equal spheres," 2016 IEEE International Symposium on Electromagnetic Compatibility (EMC), Ottawa, ON, 2016, pp. 917-920. doi: 10.1109/ISEMC.2016.7571773
Best Paper Award Finalist and Winner of Best Paper Award at DesignCon2015 for "Practical Method for Modeling Conductor Surface Roughness Using Close Packing of Equal Spheres" publication.
Best Paper Award Finalist and Winner of Best Paper Award at DesignCon2013 for “Dramatic Noise Reduction using Guard Traces with Optimized Shorting Vias” publication.
Cover story, “Practical Design of Differential Vias”, originally published for Printed Circuit Design and Fab/Circuits Assembly magazine, July 2010. (View original figures)
"Stub Termination", originally published for EDN magazine May 13, 2010.
U.S. Patent 6,091,739 granted for “HIGH SPEED DATABUS UTILIZING POINT TO MULTIPOINT INTERCONNECT NON-CONTACT COUPLER TECHNOLOGY ACHIEVING A POINT TO MULTI-POINT INTERCONNECT”
U.S. Patent 4,384, 756 granted for “Electrical Option Switch”
U.S. Patent submission for “GUIDANCE BLOCK”
U.S. Patent Submission for “REMOVABLE CARD GUIDANCE BLOCK”
U.S. Patent Submission for “METHOD AND SYSTEM FOR IMPROVING ELECTRICAL PERFORMANCE OF VIAS FOR HIGH DATA RATE TRANSMISSION”
IEEE publication, “Relative Permittivity Variation Surrounding PCB Via Hole Structures,” Signal Propagation on Interconnects, 2008. SPI 2008. 12th IEEE Workshop on , vol., no., pp.1-4, 12-15 May 2008
IEEE Publication, - "A Broadband and Parametric Model of Differential Via Holes Using Space-Mapping Neural Network", to "Microwave and Wireless Component Letter Journal", Vol. 19, Issue 09, Sept 2009
IEEE Publication, - "Differential Via Modeling Methodology", Components, Packaging and Manufacturing Technology, IEEE Transactions on, Volume: 1 , Issue: 5, May 2011
Winner of best paper award at DesignCon2009 for “Practical Analysis of Backplane Vias” publication.
2003 “Seize the Day” award for design and on time delivery of MPE 9000 midplane
2001 Silver Pride Award for design and on time delivery of Passport 20K backplane
1998 Award of Excellence team award for VSOC design for XA-Core
1995 Nortel Chairman’s award for CUSTOMERS.
1988 Award of Excellence DMS Supernode team
Awards and Publications:
Lamsim Enterprises Inc.
Innovative Signal Integrity and Backplane Solutions