Method of Modeling Differential Vias White Paper: Accurate, models for vias in a multilayer circuit board are necessary to predict link performance in the GHz regime. This white paper describes a methodology to build a high bandwidth, scalable first approximation circuit model using simple transmission lines of long vias typically used in thick backplane designs.
Practical Fiber Weave Effect Modeling White Paper: Fiber-weave effect is becoming more of an issue as bit rates continue to sore upwards to 5GB/s and beyond. Due to the non-homogenous nature of printed circuit board laminates, the fiberglass weave pattern causes signals to propagate at different speeds within differential pair traces; causing timing skew and mode conversion at the receiver; leading to reduced bit-error-rate (BER) performance; and increased EMI radiation. This white paper delves into the issue and presents a novel approach to practically establish worst case min/max values for Dk and use them to model this effect using Agilent EEof EDA circuit modeling software. A PCIe CEM Rev2 case study is used to practically demonstrate the model and to explore the design space.
Backplane Architecture High Level Design White Paper: The backplane is the key component in any system architecture. The sooner one considers the backplane’s physical architecture near the beginning of a project, the more successful the project will be. This white paper introduces the concept of a backplane High Level Design document and demonstrates the principle using a fictitious system architecture as an example.
Backplane Architecture High Level Design Slides: Example of a backplane HLD document slide deck used in Backplane Architecture High Level Design White Paper.
Guard Traces White Paper: To guard or not to guard? That is the question often asked by digital hardware design engineers. As bit rates continue to climb, there is increased debate on whether to use guard traces to control crosstalk in high-speed digital signaling. By doing so, it is believed the guard trace will act as a shield between the aggressor and victim traces. On the other hand, the argument is that merely separating the victim trace to at least three times the line width from the aggressor is good enough. This paper studies the application of guard traces and quantifies the results against non guarded scenarios.
Practical Method for Modeling Conductor Surface Roughness Using The Cannonball Stack Principle White Paper: In this paper, a practical method for modeling conductor roughness is explored. By using available data published in material data sheets alone, an equivalent multi-sphere model, based on cubic close-packing of equal spheres, also known as Cannonball Stack, is developed. To test the accuracy, a case study was done on a lossy stripline geometry based on FR408HR dielectric materials with reverse-treated copper foils.
Controlling Electromagnetic Emissions from PCB Edges in Backplanes White Paper: In this paper, the issue of electromagnetic radiation from the edges of printed circuit boards, and best practices for backplanes to reduce EMI is discussed.
Dispelling Via Stub Anxieties: Are all via stubs bad? The short answer is it depends. In this paper via stubs are explained and practical ways to quantify the answer are presented to help alleviate fears about when they may pose a problem. Rules of thumb are used and validated with a couple of examples for 28 GB/s NRZ and 56 GB/s PAM-4 signalling, using Keysight EEof EDA circuit modeling software.
Split Planes and What Happens When Microstrip Signals Cross Them: When discussing signal integrity (SI) issues there is always a great debate when signals on one layer of a printed circuit board (PCB) crossing over split or a slot in the reference planes on an adjacent layer. This white paper attempts to dispel some of the myths about signals crossing split planes.
White Papers and Documents:
Innovative Signal Integrity and Backplane Solutions
Lamsim Enterprises Inc.