Method of Modeling Differential Vias White Paper: Accurate, models for vias in a multilayer circuit board are necessary to predict link performance in the GHz regime. This white paper describes a methodology to build a high bandwidth, scalable first approximation circuit model using simple transmission lines of long vias typically used in thick backplane designs. 
Practical Fiber Weave Effect Modeling White Paper: Fiber-weave effect is becoming more of an issue as bit rates continue to sore upwards to 5GB/s and beyond. Due to the non-homogenous nature of printed circuit board laminates, the fiberglass weave pattern causes signals to propagate at different speeds within differential pair traces; causing timing skew and mode conversion at the receiver; leading to reduced bit-error-rate (BER) performance; and increased EMI radiation. This white paper delves into the issue and presents a novel approach to practically establish worst case min/max values for Dk and use them to model this effect using Agilent EEof EDA circuit modeling software. A PCIe CEM Rev2 case study is used to practically demonstrate the model and to explore the design space.

Backplane Architecture High Level Design White Paper: The backplane is the key component in any system architecture. The sooner one considers the backplane’s physical architecture near the beginning of a project, the more successful the project will be. This white paper introduces the concept of a backplane High Level Design document and demonstrates the principle using a fictitious system architecture as an example.

Backplane Architecture High Level Design Slides: Example of a backplane HLD document slide deck used in Backplane Architecture High Level Design White Paper.

Guard Traces White Paper: To guard or not to guard? That is the question often asked by digital hardware design engineers. As bit rates continue to climb, there is increased debate on whether to use guard traces to control crosstalk in high-speed digital signaling.  By doing so, it is believed the guard trace will act as a shield between the aggressor and victim traces.  On the other hand, the argument is that merely separating the victim trace to at least three times the line width from the aggressor is good enough.  This paper studies the application of guard traces and quantifies the results against non guarded scenarios.

Practical Method for Modeling Conductor Surface Roughness Using The Cannonball Stack Principle White Paper: In this paper, a practical method for modeling conductor roughness is explored. By using available data published in material data sheets alone, an equivalent multi-sphere model, based on cubic close-packing of equal spheres, also known as Cannonball Stack, is developed. To test the accuracy, a case study was done on a lossy stripline geometry based on FR408HR dielectric materials with reverse-treated copper foils.

Controlling Electromagnetic Emissions from PCB Edges in Backplanes White Paper: In this paper, the issue of electromagnetic radiation from the edges of printed circuit boards, and best practices for backplanes to reduce EMI is discussed.

Dispelling Via Stub Anxieties: Are all via stubs bad? The short answer is it depends. In this paper via stubs are explained and practical ways to quantify the answer are presented to help alleviate fears about when they may pose a problem. Rules of thumb are used and validated with a couple of examples for 28 GB/s NRZ and 56 GB/s PAM-4 signalling, using Keysight EEof EDA circuit modeling software.

Split Planes and What Happens When Microstrip Signals Cross Them: When discussing signal integrity (SI) issues there is always a great debate when signals on one layer of a printed circuit board (PCB) crossing over split or a slot in the reference planes on an adjacent layer. This white paper attempts to dispel some of the myths about signals crossing split planes.

Cannonball-Huray Model Demystified: This paper revisits the Cannonball-Huray model as it applies to the CMP-28 reference platform from Wildriver Technology and presents a detailed case study showing how to get excellent results using data sheet parameters from data sheets alone.

What Happens When Stripline Signals Cross Split Power Planes: There is often a debate in the SI community claiming, it is ok for stripline traces to cross a split power plane, so long as the other adjacent reference plane is solid; implying that the solid reference plane will return the current. Or others claim if there is an adjacent solid reference plane, less than 5mils away under the split, crosstalk will be mitigated. This white paper attempts to dispel some of the myths about signals crossing split planes.

What is Differential Impedance and Why do We Care? Simply put, differential impedance is the instantaneous impedance of a pair of transmission lines when two complimentary signals are transmitted with opposite polarity. For a printed circuit board (PCB) this is a pair of traces; also known as a differential pair. We care about maintaining the same differential impedance for the same reason we care about maintaining the same instantaneous impedance of a single-ended (SE) transmission line.  In this paper, the fundamentals and why it matters are explained.

Characteristic Impedance -Where SI/PI Worlds Collide: Signal and power integrity (SI/PI) simulations, measurements and analysis usually live in two different worlds, but occasionally these worlds collide. One such collision occurs when we refer to characteristic impedance, Z0. Traditionally the PI world lives in the frequency domain while the SI world lives in the time domain. In this paper, a novel approach to determine a uniform transmission line characteristic impedance using traditional PI measurement techniques.

Heuristic Modeling of Transmission Lines due to Mixed Reference Plane Foil Roughness in Printed Circuit Board Stackups: Designing the right printed circuit board stackup can make or break your product performance. If the product has circuitry that is impedance and transmission loss sensitive, then paying attention to conductor surface roughness is paramount. But sometimes the roughness of adjacent reference plane(s) is overlooked. If the adjacent high-speed signal layer is using smoother copper than one or both reference planes, a higher insertion loss than expected for that layer will occur and possibly cause your product to fail compliance. So how do we know this before finalizing the stackup? Since we do not have any empirical data to go by, we rely on heuristic modeling methods that rely solely on published  parameters found in manufacturer’s data sheets.

How Fiber Weave Effect Can Affect Your High-speed Design: Fiber weave effect (FWE) skew is becoming more of an issue as bit rates continue to soar upwards. As of this publication, 56 GB/s is state of the art and 112 GB/s is just around the corner; while next generation PCIe is rapidly moving to 64 GT/s. Some industry standards limit the total skew budget in a channel to 0.2UI from all sources. But is that enough for today’s PAM-4 systems? In this paper, the effect of FWE is explored on PAM-4 signalling. The analysis shows bit rates above 25 GB/s, traditional total skew budget may be insufficient for some industry standards and tighter skew budget is proposed.

A Tale of Two Data Sheets and How Foil Roughness Affects DK
: When doing stackup and impedance modeling, we need to get the dielectric material properties from the right sources. One important parameter for accurate impedance modeling is the dielectric constant or simply Dk. In this paper the difference between simple laminate suppliers’ marketing data sheets and engineering data sheets are discussed as well as how foil roughness affects the effective Dk
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